Analog-to-digital converters (ADCs) are employed in a variety of electronic systems including computer modems, wireless telephones, satellite receivers, process control systems, etc. Such systems demand cost-effective ADCs that can efficiently convert an analog input signal to a digital output signal over a wide range of frequencies and signal magnitudes with minimal noise and distortion.
An ADC typically converts an analog signal to a digital signal by sampling the analog signal at pre-determined sampling intervals and generating a sequence of binary numbers via a quantizer, wherein the sequence of binary numbers is a digital representation of the sampled analog signal. Some of the commonly used types of ADCs include integrating ADCs, Flash ADCs, pipelined ADCs, successive approximation register ADCs, Delta-Sigma (ΔΣ) ADCs, two-step ADCs, etc. Of these various types, the pipelined ADCs and the ΔΣ ADCs are particularly popular in applications requiring higher resolutions.
A pipelined ADC circuit samples an analog input signal using a sample-and-hold circuit to hold the input signal steady and a first stage flash ADC to quantize the input signal. The first stage flash ADC then feeds the quantized signal to a digital-to-analog converter (DAC). The pipelined ADC circuit subtracts the output of the DAC from the analog input signal to get a residue signal of the first stage. The first stage of the pipelined ADC circuit generates the most significant bit (MSB) of the digital output signal. The residue signal of the first stage is gained up by a factor and fed to the next stage. Subsequently, the next stage of the pipelined ADC circuit further quantizes the residue signal to generate a further bit of the digital output signal, with this process being repeated for each stage of the ADC circuit.
On the other hand, a ΔΣ ADC employs over-sampling, noise-shaping, digital filtering and digital decimation techniques to provide high resolution analog-to-digital conversion. One popular design of a ΔΣ ADC is a multi-stage noise shaping (MASH) ΔΣ ADC. A MASH ΔΣ ADC is based on cascading multiple first-order or second-order ΔΣ ADCs to realize high-order noise shaping.
While both pipelined ADCs and ΔΣ ADCs provide improved signal-to-noise ratio, improved stability, etc., the performance of both pipelined ADCs and ΔΣ ADCs is bottlenecked by the linearity of the internal DAC. For example, the gain error of a DAC used in the first stage of a pipelined ADC circuit contributes to the overall gain error of the pipelined ADC circuit. The gain error of an ADC can be defined as the amount of deviation between an ideal transfer function and a measured transfer function of the ADC. One method used to overcome the limitations imposed by the gain errors of various stages of ADCs is to digitally calibrate the gain errors using calibration filters.
An illustration of a known pipelined ADC circuit 10 calibrated for gain errors using a calibration filter is shown in FIG. 1. The pipelined ADC circuit 10 converts an analog input signal u into a digital output signal y. While a typical pipelined ADC circuit may consist of several ADC stages, the pipelined ADC circuit 10 is shown to have a first stage 12 and a backend ADC labeled ADC2 14, where ADC2 14 may include one or more subsequent stages. The first stage 12 includes an ADC labeled ADC1 16 and a digital-to-analog converter (DAC) labeled DAC1 18. The ideal gain of the first stage 12 is G as represented by an amplifier block 20. The first stage 12 partially quantizes the analog input signal u to provide a digital output d1. The digital output d1 is converted to an analog signal by DAC1 18 and subtracted from the input signal u to generate an error signal e. Subsequently, the error signal e is amplified by the ideal gain G within the amplifier 20 to generate an analog residue signal r of the first stage of the ADC circuit 10. The analog residue signal r is input to the ADC2 14 for further quantization. The quantization error of ADC1 16 is assumed to be q1 and the quantization error of ADC2 14 is assumed to be q2.
The pipelined ADC circuit 10 also includes a pseudo-random signal generator 22 that generates a pseudo-random signal dt (also known as a dither signal). The pipelined ADC circuit 10 uses the signal dt for calibrating the gain errors. The signal dt is amplified by ¼ and is added to the digital output of ADC1 16. The combined output of the ADC1 16 and dt which is represented by d1, is input to the DAC1 18. Thus the signal dt flows through part of the first stage 12 and the ADC2 14 to the digital output signal y of the pipelined ADC circuit 10.
The pseudo-random signal dt, the first stage digital output d1, and the final digital output y are input into a calibration filter 24, which compares the pseudo-random signal dt to the digital output signal y. In a perfectly calibrated ADC circuit, there should be no residue of the pseudo-random signal dt in the output signal y. Therefore, based on the amount of traces of the pseudo-random signal dt signal found in the output signal y, the calibration filter 24 adjusts a calibration co-efficient l0 of a multiplier 26. A perfect calibration is obtained when there are no traces of the pseudo-random signal dt in the digital output signal y. The calibration filter 24 functions in an iterative fashion by monitoring the digital output signal y and correlating it with the pseudo-random signal dt. Such correlation is generally performed using various components including a delay circuit 28, a correlator 30, an accumulator 32 and a digital quantizer 34.
While the calibration filter 24 used with the pipelined ADC circuit 10 of FIG. 1 calculates only the calibration coefficients related to gain errors of the pipelined ADC circuit, calibration filters used with other types of ADC circuits may calculate various other calibration coefficients. For example, a calibration filter used with a ΔΣ ADC circuit calculates calibration coefficients related to a gain and an integrator pole of a first stage of the ΔΣ ADC circuit using an iterative algorithm similar to the one described above.
One of the disadvantages with the implementations of calibration filters using an iterative algorithm described above is the long time, usually on order of million clock cycles, that is necessary for the calibration filters to converge to a correct set of filter coefficients. Specifically, the calibration filter 24 may have to iterate several million clock cycles before it converges on the ideal calibration settings for the pipelined ADC circuit 10. Moreover, because the correlator 30 of the calibration filter 24 is effected by the analog input signal u, to suppress the effect of the analog input signal u, the output of the correlator 30 is accumulated over several thousands of samples by the accumulator 32. Therefore, in a start-up phase of an ADC circuit using a calibration filter, a large number of measurements are required before the calibration filter converges. As a result, the total startup time for such a calibration filter may become exceedingly long.
Such a long startup time for computation of calibration coefficients results in a requirement for longer testing time for circuits using ADC components, sometimes over a minute for each component, which is a major problem for volume production of circuits using ADC components. To facilitate volume production of circuits using ADC components at a reasonable cost, it is necessary to reduce the startup time required for ADC calibration filters.